The present invention relates to a MOS device, such as a MOS transistor or a MOS capacitor, and more specifically to a semiconductor device containing MOS devices having their respective gate electrodes made of a metal or metal compound and a method of manufacture thereof.
In recent years, as a key component of computers and communications equipment use is extensively made of a large-scale integrated circuit or circuits (LSI circuits) in which a very large number of transistors and resistors are integrated into a single chip so that they are interconnected to implement electronic circuitry. For this reason, the performance of the whole equipment depends largely on the performance of the LSI circuit. The performance of the LSI circuit can be upgraded by increasing the packing density, namely, scaling down the dimensions of the MOS devices (microstructuring of the MOS devices).
For example, in the case of MOS transistors, the microstructuring of devices can be realized by reducing the gate length and making source/drain diffusion layers small in thickness.
As a method of forming shallow source/drain diffusion layers, low-acceleration ion implantation is widely used, by which source/drain diffusion layers having a thickness of less than 0.1 xcexcm can be formed.
However, the source/drain diffusion layers formed by the low-acceleration ion implantation have a high sheet resistance as high as 100xcexa9/xe2x96xa1. Thus, an increase in the speed of circuit operation owing to microstructuring cannot be expected without modification.
With devices having high speed requirements, such as logic LSI circuits, the salicidation technology is used by which a silicide film is formed on source/drain diffusion layers and the top of the gate electrode made of a polycrystalline silicon (hereinafter referred to as polysilicon) film doped with impurities using a self-aligned process.
In the formation of dual-gate MOS transistors (n-channel and p-channel MOS transistors formed in the same substrate: the n-channel transistor has a gate electrode made of n-type doped polysilicon and the n-channel transistor has a gate electrode made of p-type doped polysilicon), the salicidation technology can effect not only a reduction in the resistance of gate electrodes but also a decrease in the number of manufacturing steps.
The reason is that, in the ion implantation step of forming source/drain diffused regions, the gate can be doped with impurities of given conductivity type.
In contrast, in the formation of dual-gate MOS transistors having a polycide (polysilicon-silicide) gate electrode in which a metallic silicide film is formed onto a polysilicon film doped with impurities, the polysilicon film cannot be doped with impurities of given conductivity type in the ion implantation step for forming source/drain regions because it is masked by the metallic silicide film.
Therefore, prior to the formation of source/drain regions it is required to dope the polysilicon film with impurities of given conductivity type. That is, the ion implantation step for forming the source/drain regions and the ion implantation step for doping the polysilicon film with impurities have to be carried out separately, increasing the number of steps.
To be specific, in comparison with the salicide process, the polycide process requires two additional steps for each of photolithography, ion implantation, and resist stripping.
On the other hand, with devices that require devices to be packed as closely as possible as in memory LSI circuits such as DRAMs, it is essential to adopt SAC (Self-Aligned Contact) structures.
The formation of the SAC structure involves a step of etching an interlayer insulating film on one of the source/drain diffusion layers (usually one used as the source) by means of RIE (Reactive Ion Etching) to form a contact hole to the source/drain diffusion layer.
At this point, even if the contact hole is misaligned, it is required not to expose the top of the polysilicon gate electrode. To this end, a silicon nitride film is formed in advance on the gate electrode as an etching stopper film.
The presence of such a silicon nitride film will not allow impurities to be introduced into the gate electrode in the ion implantation step for the formation of the source/drain regions. For this reason, unlike the logic LSI, in the memory LSI, the salicidation technology cannot be used.
Heretofore, gate electrodes made of impurity-doped polysilicon (polysilicon gate electrodes) have been widely used. In addition, the polycide gate electrodes have also been used to comply with low-resistivity requirements.
Where gate electrodes of much lower resistivity are required, a poly-metal gate electrode structure is used in which an impurity-doped polysilicon film, a barrier metal film and a tungsten (W) film are stacked in sequence. The poly-metal gate electrode, which is lower in resistivity than the polycide gate electrode, can implement a desired sheet resistance with reduced film thickness.
However, the poly-metal electrode has the following problem: As described previously, the dual-gate structure is used in logic LSI circuits. As with the use of the polycide gate structure, the use of the poly-metal gate electrode structure in logic LSI circuits requires two separate steps: a step of ion implanting impurities into the polysilicon film of the poly-metal gate electrode, and a step of ion implanting impurities into the silicon substrate to form the source/drain regions. This thus results in an increase in the number of steps and an increased in manufacturing cost.
In an LSI circuit having a logic IC and a DRAM built in, the formation of a silicide film onto the top of the source/drain diffusion layers in the DRAM results in an increase in the current leakage in pn junctions of memory cells, degrading the data holding property of the cells. In the DRAM, which requires the SAC structure as described previously, a W polycide electrode is used.
On the other hand, for the DRAM to allow as much current as possible to flow with a low voltage, it is required to lower the threshold voltage of MOS transistors. To this end, it is required to dope the polysilicon film in the gate electrodes of n-channel MOS transistors with n-type impurities such as phosphorous (P) or arsenic (As) and dope that of p-channel MOS transistors with p-type impurities such as boron (B).
Here, in the DRAM, the thermal budget (determined by time and temperature) after the formation of the gate electrodes is great. Therefore, the use of the polysilicon films doped with such impurities for gate electrodes (polycide gate electrodes) poses two problems in the thermal process subsequent to the formation of the gate electrodes.
The first problem results from that, in the thermal process subsequent to the formation of the gate electrodes, the impurities, such as P or As, doped into the polysilicon film diffuse outward into the W silicide film and results in a decrease in the impurity concentration in the polysilicon film.
When the impurity concentration in the polysilicon film is decreased, the depletion layer spreads into the gate electrode when it is impressed with a gate voltage. As a result, the actual gate capacitance becomes smaller than the gate capacitance defined by the gate insulating film by the amount corresponding to the depletion layer. That is, the first problem is that the threshold voltage of the MOS transistors deviates from the designed value.
The second problem results from that, in the thermal process subsequent to the formation of the gate electrodes, the impurities, such as B, penetrate through the gate oxide into the silicon substrate.
The penetration of B through the gate oxide into the silicon substrate results in a change in the distribution of impurity concentration in the channel region. In this case as well, the problem arises in that the threshold voltage deviates from the designed value.
The penetration of B (inward diffusion of B) is promoted by doping the gate oxide with fluorine (F) or hydrogen (H) but controlled by doping the gate oxide with nitrogen (N). The reason why the penetration of is controlled by doping of N is that strong Bxe2x80x94N bonds are formed at the interface of the polysilicon film and the gate oxide. However, the effect of controlling the penetration of B by doping of B was poor.
To summarize, since the MOS transistors in the memory LSI circuit and the MOS transistors in the logic LSI circuit have different requirements, there are a problem that a common gate electrode-structure cannot be used in the memory LSI circuit and the logic LSI circuit and a problem that depletion occurs in the polycide gate electrodes or poly-metal gate electrodes, especially in the memory LSI circuit, or the threshold voltage varies due to diffusion of impurities (i.e., the threshold voltage varies from device to device).
It is an object of the present invention to provide a semiconductor device which comprises MOS devices each having its gate electrode made of a metal or metallic compound that permits variations in device characteristics to be controlled and a method of manufacture thereof.
To attain the object, a semiconductor device of the present invention comprises: a semiconductor region; a gate insulating film formed on the surface of the semiconductor region; and a first gate electrode formed on the gate insulating film and containing a metal in its portion that contacts the gate insulating film, the average grain size in the portion of the first gate electrode being 30 nm or less.
When the grain size is 0 nm, the portion of the gate electrode that contacts the gate insulating film is amorphous. When the grain size is larger than 0 nm and smaller than 30 nm, the portion is microcrystalline. In the present invention, a crystal particle size 0 nm is defined as an amorphous one.
The semiconductor region is, for example, a silicon substrate or a semiconductor layer formed on the silicon substrate.
A second gate electrode may be formed on the first gate electrode, which is lower in resistivity than and larger in grain size than the first gate electrode.
The first gate electrode is, for example, the gate electrode of a MOS transistor or a MOS capacitor.
The portion of the first gate electrode that contacts the gate insulating film is made of at least one of nitride, carbon nitride, silicon nitride of transition metal elements in IV group, silicon nitride of transition metal elements in V group, silicon and nitride of transition metal elements in VI group.
Specifically, the portion of the first gate electrode that contacts the gate insulating film is made of at least one of W nitride, Mo nitride, Ta nitride, Ti nitride, W silicon nitride, Mo silicon nitride, Ta silicon nitride, Ti silicon nitride, Ti carbon nitride, W carbon nitride, Mo carbon nitride, and Ta carbon nitride.
Moreover, the portion of the first gate electrode that contacts the gate insulating film may be made of at least one of oxygen-containing Ru, nitrogen-containing Ru, and nitrogen-containing RuO2. Furthermore, the portion may be made of oxygen- or nitrogen-containing Pt or Ir or nitrogen-containing Ir2O3.
A semiconductor device manufacturing method of the present invention comprises the steps of: forming a first gate insulating film on the surface of a semiconductor substrate; forming a dummy gate electrode pattern on the first gate insulating film; forming an interlayer insulating film on the semiconductor substrate so as to cover the dummy gate electrode pattern; processing the surface of the interlayer insulating film until the dummy gate electrode pattern is exposed; removing the dummy gate electrode pattern and the underlying first gate insulating film to thereby form an opening in the interlayer insulating film; forming a second gate insulating film on the exposed surface of the semiconductor substrate on the bottom and on the sidewall of the opening; forming a first gate electrode on the second gate insulating film within the opening so that space is left inside the opening, the first gate electrode containing a metal and having an average grain size of 30 nm or less; forming, on the surface, a conductive film lower in resistivity than and larger in average grain size than the first gate electrode so as to fill in the space within the opening; and removing the conductive film outside the opening to thereby form a second gate electrode consisting of the conductive film within the opening.
Here, it is preferable to remove the conductive film outside the opening by either mechanical/chemical polishing or mechanical polishing.
In addition, it is preferable to carry out steps after the formation of the first and second gate electrodes at temperatures of 750xc2x0 C. or below.
Our studies have made clear that, with the use of a gate electrode in which its portion that contacts the gate insulating film contains a metal and the average grain size is 30 nm or less, variations in threshold voltage of MOS transistors and variations in capacitance of MOS capacitors can be prevented. For example, variations in threshold voltage could be reduced to one seventh or less of the conventional value.
Since the average grain size is 30 nm or less, the stress in the film can be reduced (for example, 500 MPa or less). Thus, the hot-electron resistance can be reduced and the device reliability can be increased.
The use of the materials according to the present invention permits a gate electrode to be formed easily, in which its portion that contacts the gate insulating film contains a metal and has an average grain size of 30 nm or less. Thus, MOS devices that have the above-described characteristics can be implemented with ease.
According to the manufacturing method of the present invention using a dummy gate-electrode pattern, the accuracy of the gate length is determined by the accuracy of the dummy gate electrode pattern. Since the dummy gate electrode pattern is not used as an actual gate electrode, it can be made of impurity-free silicon or silicon oxide. These silicon-based materials can be processed by RIE more accurately than metals. Therefore, the accuracy of the gate length can be improved and variations in gate length can be reduced (e.g., 20 nm) through the use of such a material.
By removing the conductive film outside the opening by means of mechanical/chemical polishing or mechanical polishing, the dimension of the second gate electrode in the direction of height can be controlled with accuracy, reducing variations in the dimension in the direction of height.
By carrying out processes after the formation of the first and second gate electrodes at temperatures of 750xc2x0 C. or below, it was found that the degradation of device characteristics can be prevented effectively.
In order to achieve this advantage for MOS transistors, it is recommended to form source/drain diffusion layers using the dummy gate electrode pattern as a mask and then form the first and second gate electrodes.
By so doing, it becomes possible to prevent an increase in gate leak current and an increase in variations in threshold voltage which are due to the source/drain formation process that involves a process temperature above 750xc2x0 C.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.